For its high-density, the DRAM (Dynamic Random Access Memory) is utilized extensively as a main memory in computer systems, even though it requires refresh cycle to sustain stored data within a predetermined refresh time. As such, the DRAM constitutes a key component that holds sway on the performance of the computer system. Efforts of research and development have been under way primarily to boost the density and also speed improvement.
In the conventional DRAM, hierarchical bit line architecture is applied to achieve high-speed operation, as published, “Hierarchical bitline DRAM architecture system” as U.S. Pat. No. 6,456,521, and “A hierarchical bit-line architecture with flexible redundancy and block compare test for 256 Mb DRAM” in VLSI Circuits, Digest of Technical Papers, May 1993. pp 93-94. More specifically, FIG. 1 illustrates a circuit diagram of the conventional DRAM. The memory cells 101 and 102 are connected to a local bit line 131, and the memory cells 103 and 104 are connected to another local bit line 133, where the plate of capacitor is connected to half supply voltage typically. Local bit lines 131 and 133 are connected to a global bit line 111 and another global bit line 112 through transfer transistors 121 and 123, respectively. And more local bit lines 132 and 134 are connected to the global bit lines 111 and 112, respectively. When reading, one of memory cells is selected, and the selected cell charges or discharges the local bit line while the local bit lines and the global lines are released from pre-charge node 117, such that equalizer transistor 113, pre-charge transistors 114 and 115 are turned off by a control signal 116. Thus, one of global bit lines is also charged or discharged by the selected memory cell. After then sense amp 141 is activated to generate a read output 142. However, the selected global bit line is slowly changed because the selected memory cell should drive local bit line and global bit line through transfer transistor, where the global bit line increases total capacitance. Moreover, the storage capacitor in the memory cell should be relatively big in order to absorb the charges from the global bit line, which is one of major obstacles to reduce the DRAM cell. As a result, access time is also slow because of heavy global bit line, which increases propagation delay and sensing time for the sense amp.
And there is a prior art for improving DRAM with adding a local sense amp, as published, “High speed DRAM local bit line sense amplifier”, U.S. Pat. No. 6,426,905, wherein the local sense amplifier detects a change of charge out of an input node, and comprises a first current source and a first field effect transistor. The current source is provided for removing charge from the input node. The field effect transistor includes (i) a source coupled to the input node, (ii) a gate electrode coupled to a first voltage, and (iii) a drain coupled to one side of a first capacitor, to an output node, and to a pre-charge circuit for setting the voltage of the output node to a second voltage, providing a voltage difference between the drain and source of said first transistor. The other side of the capacitor is coupled to ground. However, many transistors (total 11 transistors) for each local sense amplifier are required, such that chip area is sacrificed for the improvement.
And more prior arts are shown for dividing the bit line into short lines, “A 322 MHz Random-Cycle Embedded DRAM With High-Accuracy Sensing and Tuning”, IEEE Journal of Solid-State Circuits, Vol. 40, No. 11, November, 2005, and “A 500 MHz Random Cycle 1.5 ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier”, IEEE International Solid-State Circuits Conference, pp. 486, 2007. However, those prior arts still use conventional differential sense amplifier for reading data from the memory cell. In consequence, the area of the chip is increased more, which is one of obstacles for realizing very high density and high speed memory.
Furthermore, memory cell structure of the conventional DRAM includes a cup-like capacitor as published U.S. Pat. No. 7,183,603 and a deep trench capacitor as published U.S. Pat. No. 6,608,341. Hence, scaling the big storage capacitor is one of major obstacles, because total storage capacitance should be maintained around 20-30 fF for reading the memory cell through a heavy bit line and also retaining data within same or longer refresh time. In order to avoid forming the big storage capacitor, sensing scheme should be improved to read a reduced capacitor memory cell, which also should improve access time. And in order to retain data for long time even though the capacitor is reduced, leakage current of the memory cell should be reduced with pseudo negative word line scheme. More detailed explanation will be described as below.